Turtle logic : Novel IC digital probabilistic design methodology

With the progress on VLSI process technology, the design complexity and the transistor density in system increases rapidly, causing that the power consumption and power density in system rise with the same trend. The size of CMOS devices is scaled down to the nanoscale level where interferences (soft-errors), becoming significant, affect the VLSI circuit performance [1]. Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates [1]. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique [2]. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF) [3]. [4] Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.